1. Field of the Invention
The present invention relates to a regulator circuit which maintains stable output voltage.
2. Description of the Related Art
In order to maintain stable operation of an electronic circuit, there is a demand for maintaining a stable power supply voltage at a constant value. Also, an apparatus mounting such electronic circuits does not always include a power supply voltage necessary for each of such electronic circuits. For example, a 5V microcomputer mounted in an automobile requires a power supply voltage of 5 V. However, a battery mounted in the automobile can only supply an unstable voltage of 12 V to such a 5V microcomputer mounted in the automobile. With such an arrangement, a regulator circuit is widely used in order to generate by means of a simple configuration a stable power supply voltage necessary for such an electronic circuit.
In general, such a regulator circuit includes an error amplifier, an output transistor, and a feedback resistor. The error amplifier has a function of making a comparison between a desired reference voltage value and the output voltage input as a feedback signal via the feedback resistor. Furthermore, the error amplifier has a function of controlling the voltage applied to the control terminal of the control circuit such that these two voltages thus compared approach each other. With such an arrangement, in a case that there is a change in the input voltage or a change in the load, there is a need to adjust the voltage applied to the control terminal of the output transistor according to the change in the input voltage or the change in the load.
In some cases, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is employed as the output transistor in order to provide reduced current consumption. Let us consider an arrangement employing such a MOSFET as the output transistor. With such an arrangement, in order to provide a large current capacity, there is a need to increase the transistor size. This leads to a large gate capacitance, leading to a response delay of the gate voltage, which is controlled by the error amplifier, with respect to the change in the input voltage or the change in the load. This response delay leads to the output voltage being overshot or undershot. Also, with such an arrangement, the output voltage being thus overshot or undershot occurs due to the change in the load, i.e., the change in the output current.
In order to solve such a problem, a technique has been proposed in which the current that flows through the load from the output transistor is monitored, and the bias current applied to the error amplifier is increased according to the current thus monitored, thereby increasing the response speed of the regulator.
[Patent Document 1]
Japanese Patent Application Laid-open No. 2001-34351
With an arrangement employing the technique described in the aforementioned document, in a case that a great amount of current flows through the load, a great amount of bias current flows through the error amplifier, thereby providing the regulator circuit with an increased response speed. However, in a case that the current that flows through the load is rapidly reduced, the response speed is reduced due to the reduction in the current. In some cases, such a reduction in the response speed leads to an undesired fluctuation in the output voltage. Furthermore, such an arrangement has a problem of difficulty in suppressing the fluctuation of the output voltage occurring due to the fluctuation of the input voltage.